The fabrication of an integrated circuit normally begins by processing the semiconductor substrate or wafer to divide the surface area into regions where active devices and substrate embedded interconnects are to be formed, and other regions of dielectric which electrically separate the active regions. The field oxide dielectric material is routinely silicon dioxide. Though various field oxide formation techniques have been developed and described, the technique commonly known as the localized oxidation of silicon (LOCOS) remains common within the semiconductor industry. In the practice of LOCOS, the active regions of the silicon substrate are masked by a silicon nitride layer, while the field oxide regions are thermally oxidized to form a field dielectric region. Though fundamentally simple and efficient, the LOCOS process, and its progeny, such as the FUROX and SWAMI techniques, exhibit deficiencies which reduce yield or performance in the final semiconductor chip product.
The most frequently encountered deficiency in the prior art techniques is commonly known as the bird's beak problem, wherein the field oxide extends under the masking nitride layer to consume some of the usable active area. Additional problems routinely encountered with known field oxide formation processes include stress induced dislocations at the edges of the active region, and the presence of a relatively nonplanar surface in or adjacent the fully formed field oxide. The nonplanar recesses or notches at the edges of the active region often degrade subsequently formed gate oxide, which can trap conductive layer residuals creating short circuit paths. Solutions to these problems have been proposed, but routinely involve relatively complex or dimensionally critical fabrication sequences which are costly to practice or degrade the semiconductor chip yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently most relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. Nos. 3,958,040; 4,398,992; 4,088,516; 4,333,965; 4,563,227; 4,564,394; 4,622,096 and 4,631,219. Relevant technical literature includes the article entitled "Isolation Technology For Scaled MOS VLSI" by Oldham, which appeared as paper 9.1 in IEDM 82, pages 216-219; the article entitled "A Bird's Beak Free Local Oxidation Technology Feasible For VSLI Circuits Fabrication" by Chiu et al., which appeared in the IEEE Transactions On Electron Devices, pages 536-540, April 1982; the article entitled "The Sloped-Wall SWAMI--A Defect-Free Zero Bird's-Beak Local Oxidation Process For Scaled VLSI Technology" by Chiu et al., which appeared in the IEEE Transactions On Electron Devices, pages 1506-1511, November 1983; the article entitled "Defect Characteristics And Generation Mechanism In A Bird Beak Free Structure By Sidewall Masked Technique" by Fang et al., which appeared in the Journal of Electrochemical Society, pages 190-196, 1983; the article entitled "A New Fully Recessed-Oxide (FUROX) Field Isolation Technology For Scaled VLSI Circuit Fabrication" by Tsai et al., which appeared in the IEEE Electron Device Letters, pages 124-126, February 1986; the article entitled "A Method For Saving Planar Isolation Oxides Using Oxidation Protected Sidewalls" by Kahng et al., which appeared in the Journal of Electrochemical Society, pages 2468-2471, November 1980; the article entitled "The SWAMI--A Defect Free And Near-Zero Bird's-Beak Local Oxidation Process And Its Application In VLSI Technology" by Chiu et al., which appeared as pages 9.3 in IEDM 82, pages 224-227, 1982; the article entitled "Defect Free Process Of A Bird's Beak Reduced LOCOS" by Inuishi et al., which appeared as Abstract No. 273 in an unknown publication, pages 409-410, of 1985 or later date; and the article entitled "Optimization of Sidewall Masked Isolation Process" by Teng et al., which appears in IEEE Journal of Solid-State Circuits, pages 44-51, February 1985. The diversity and complexity of the various technical approaches substantiates the difficulty and importance of developing a commercially viable process for isolating active regions in a silicon substrate during the fabrication of integrated circuits.
Though a number of the techniques successfully attack and solve the bird's beak problem, and usually provide relatively planar final concluding surfaces, the approaches routinely create stress induced dislocations at the edges of the active regions, and form topologies which include notches or grooves of sufficient dimension to cause the degradation of subsequently formed gate oxide. The stress induced dislocations are often not even recognized, while the notches or grooves are most often visible in the SEM cross-sections of the final structures.
A process which overcomes many if not most of the problems encountered by the prior art processes is known as recessed sealed sidewall field oxidation (RESSFOX). The RESSFOX process is disclosed in U.S. Pat. No. 4,923,563. In brief, the RESSFOX process utilizes a relatively thick pad oxide below a first masking nitride layer. A second, very thin, masking nitride layer is applied to the sidewall of an etched opening to define the lateral boundaries of a field oxide region. The thin sidewall masking nitride layer does not utilize an underlying pad oxide layer although it may include a thin underlying screening oxide. Upon oxidation, the thin sidewall nitride is concurrently lifted and converted to oxide, the materials and dimension being selected to ensure that when the field oxide level approaches the level of the thick pad oxide layer stresses at the corners of the active silicon region are relieved through various oxide paths and accentuated oxidation effects.
After the field oxide growth, and in preparation for the formation of active devices, the substrate in the active regions is exposed. This is achieved by removing a topmost oxidized nitride layer (formed during the field oxide growth), such as by etching with HF. The first masking nitride layer is then removed with an acid such as a hot H.sub.3 PO.sub.4, and the pad oxide is removed by a chemical (HF) etch. Of course, a portion of the field oxide is also removed each time an oxide layer is removed by a chemical etch. If the etching chemical remains too long on the surface of the chip, overetching of the field oxide occurs and a corner of the substrate is exposed on the boundary of the field oxide region. The gate oxide for the active devices is then grown on the surface of the resulting structure. Under carefully controlled processing, the structure underlying the gate oxide is well suited for gate oxide growth. However, if corners are exposed by overetching, a thinning of the subsequently grown gate oxide can occur which can create integrity/reliability problems for the resulting chip.